Neat project - there are already a couple of good open FPGA projects. Have a look at Dirk Koch's and the FABolous teams work. They are doing exceptional work.
But all open FPGA projects miss the IO required for a good design. They do not have any serdes hardware nor DDR IO cells.
LarsKrimi 3 hours ago [-]
This project seems to have a serdes block which seems to wrap whatever is in the PDK. Didn't look too far down but from a cursory glance it looked like it was built for an internal clock of 50 MHz (clock default to 20 ns) with an oversampling of 8: 400 MHz
If those numbers are at all right it puts it in useful territory. Very much so for a first spin
For a first spin it looks overall pretty useful. The only nitpick I have would be that `operation` on the DSP tile should be from fabric instead of config (hardcoded in bitstream) otherwise I don't see a convenient way of resetting the accumulator(?)
__patchbit__ 3 hours ago [-]
[flagged]
dizhn 2 hours ago [-]
There's also an open source Authenticator software with the same name.
blowback 4 hours ago [-]
Excellent. Put me down for a couple.
Rendered at 13:03:25 GMT+0000 (Coordinated Universal Time) with Vercel.
But all open FPGA projects miss the IO required for a good design. They do not have any serdes hardware nor DDR IO cells.
If those numbers are at all right it puts it in useful territory. Very much so for a first spin
For a first spin it looks overall pretty useful. The only nitpick I have would be that `operation` on the DSP tile should be from fabric instead of config (hardcoded in bitstream) otherwise I don't see a convenient way of resetting the accumulator(?)